AutoESL
Company

Last deal

$2M

Amount

Seed

Stage

22.04.2010

Date

1

all rounds

$2M

Total amount

General

About Company
AutoESL provides high-level synthesis tools for FPGA and ASIC design applications.

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Also Known As

AUTOESL DESIGN TECH INC

founded date

01.01.2006

Number of employees

Company Type

For Profit

Last funding type

Seed

IPO status

Private

Description

The company's tools include AutoPilot ASIC, which generates RTL for ASICs that produces quality results for the architecture that is being targeted, and AutoPilot FPGA, an architecture-aware synthesis tool for FPGAs that uses functions, memories, and cores available in the FPGA devices. The platform is used for digital signal processing, security, scientific computing, FPGA-based emulation, network processing, and high-performance computing applications. AutoESL also offers training and support services. The company was founded in 2006 and is based in Cupertino, California. It became a subsidiary of Xilinx Inc. in 2011.
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